The present invention relates generally to improved apparatus and methods for controlling the operation of digital data processors.
In the above mentioned concurrently filed application Ser. No. 08/174/856, a highly advantageous high speed microinstruction execution architecture is disclosed which is preferably implemented on a single integrated circuit chip or module and which is capable of employing CISC and RISC instructions with multistage pipelining and branch prediction. The present invention provides a very significant and novel enhancement of the approach disclosed in this application which is likewise preferably implemented on a single integrated circuit chip or module and which is also applicable to a wide variety of other architectures.
The novel enhancement provided by the present invention adds the very important capability of permitting speculative changes of state to occur during execution of a predicted instruction before it is determined whether or not the instruction was correctly predicted. As is well known by those skilled in the art, permitting changes of state for a possibly incorrect instruction is considered to be undesirable, because of the problems associated with having to undo the incorrect state changes, which is an even more difficult problem where a multistage architecture is employed, as in the aforementioned concurrently filed patent application.
In accordance with the present invention, methods and apparatus are provided which permit speculative changes of state to be made during execution of a predicted instruction before the correctness of the prediction has been determined, while also providing for correcting the incorrectly changed state in a highly advantageous and expeditious manner if it is determined that the invention was mispredicted.
The specific nature of the invention as well as other objects, features, advantages and uses thereof will become evident from the following detailed description of a preferred embodiment in conjunction with the accompanying drawings.